Typical fastest setup (80MHz with 1x divide, 20x multiply, 2 x divide)

Using an 8MHz crystal


#pragma config FPLLIDIV = DIV_2 //PLL Input Divider (Must produce 4-5MHz from crystal frequency)
#pragma config FPLLODIV = DIV_1 //PLL Output Divider
#pragma config FPLLMUL = MUL_20 //PLL Multiplier

//SYSTEMConfigPerformance(80000000ul); //Note this sets peripheral bus to '1' max speed (regardless of configuration bit setting) //Use PBCLK divider of 1:1 to calculate UART baud, timer tick etc

Reduced speed of 40MHz to reduce power consumption (40MHz with 2 x divide, 20x multiply, 2 x divide)


#pragma config FPLLIDIV = DIV_2 //PLL Input Divider (Must produce 4-5MHz from crystal frequency)
#pragma config FPLLODIV = DIV_2 //PLL Output Divider
#pragma config FPLLMUL = MUL_20 //PLL Multiplier

SYSTEMConfigPerformance(40000000ul); //<<

Reduced speed of 20MHz to reduce power consumption (20MHz with 2x divide, 20x multiply, 4 x divide)


	#pragma config FPLLIDIV = DIV_2			//PLL Input Divider
	#pragma config FPLLODIV = DIV_4			//PLL Output Divider
	#pragma config FPLLMUL = MUL_20			//PLL Multiplier

	SYSTEMConfigPerformance(20000000L);		//Note this sets peripheral bus to '1' max speed (regardless of configuration bit setting)

 

 

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