//= 80MHz with /2, x32, /2 PLL
//= 25nS per instruction
//How it works:
//Input OSC = 10MHz (1.6 MHz to 16MHz required)
//10MHz / 2 = 5MHz (0.8 MHz to 8 MHz required)
//PLLFBD = 30 = x32 = 160MHz (100 MHz to 200 MHz required)
//CLKDIV 7:6 = 0 = \2 = 80MHz (12.5 MHz to 80 MHz requried, which generates device operating speeds of 6.25-40 MIPS).
//PLLDIV = /2 = 4MHz (4MHz required for 96MHz PLL if used)
//This generates 96MHz internally
//CPDIV = /1 (we don't set it and that is default)
//Then there is a fixed /3 divider.
//So we get 32MHz out.
//The processor clock source is divided by two to produce the internal instruction cycle clock (Fcy = Fosc/2)
//So we have 16MIPS / 16MHz clock for instruction execution and peripherals.
//= 62.5nS per instruction