Interrupt Priority Level

1 (lowest) to 7 (highest)

Multi Vector / Single Vector Interrupts

	//----- ENABLE INTERRUPTS -----

Interrupt Functions

New Style

void __ISR(_TIMER_5_VECTOR, IPL7SRS) Timer5IntHandler(void) 	//(<<<<<<< IPL# must match the priority level assigned to the irq where its enabed, Use 'SRS' if config FSRSSEL is assigned to same level, or use 'SOFT' if not)


For many PIC32 devices you can specify in the configuration-bit settings an interrupt priority level that will use a special fast shadow register set (e.g. FSRSSEL=PRIORITY_7 "SRS Select").  For these devices you need to specify which context-saving mechanism to use for each interrupt handler:

Some PIC32 variants may have 8 register sets (1 standard set and 7 shadow register sets) meaning that there are enough shadow register sets for every interrupt priority level. For these you should use the IPLnSRS IPL specifier for every interrupt service routine.

Where there is only 1 shadow register set:

For interrupt service routines set to the interrupt priority level which has been assigned the shadow register set, use IPLnSRS.

For all other interrupt service routines use IPLnSOFT.

Use IPLnAUTO to have the compiler generate code that determines the shadow register set assignment at runtime (slower).   The compiler defaults to using IPLnAUTO when the IPL specifier is omitted from the interrupt() attribute.

SRS has the shortest latency, SOFT has a longer latency due to registers saved on the stack and AUTO adds a few cycles to test if SRS or SOFT should be used.

Old Style

void __ISR(_TIMER_5_VECTOR, ipl7) Timer5IntHandler(void) 	//(ipl# must match the priority level assigned to the irq where its enabed)

This will generate a depreciated warning like "warning: Interrupt priority IPL7 is deprecated. Specify as 'IPL7{AUTO|SOFT|SRS}' instead."


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